The present invention relates to a miniaturized image acquisition apparatus which is suitable, in particular, for recording fingerprints.
Automatic recognition of an image with a typical structuring, such as for instance in the case of a fingerprint, requires not only a unit for recording the image but also a unit for processing the image and for extracting significant constituents, such as the minutiae which are characteristic of a fingerprint. Previous solutions, one of which is described in IBM Technical Disclosure Bulletin 17, 406-407 (1974), require complicated circuits which take up a great deal of space and energy. Therefore, sensor units separate from the processing and evaluation unit have been used for recording small images such as for example fingerprints. The sensor units comprise a multiplicity of individual sensor elements arranged in a grid. The processing unit usually comprises a microcontroller and/or a digital signal processor. However, such hybrid systems are too expensive for application as a mass-produced product, which means that such constructions are too costly for a host of areas of application. The algorithms for evaluating the acquired image are often very complicated, e.g. in particular when, as in the above-mentioned IBM TDB, what is involved is extracting particular characteristics of the recorded image and comparing them with references.
Fitz and Green, in xe2x80x9cFingerprint Pre-Processing on a Hexagonal Grid,xe2x80x9d published in European Convention on Security and Detection, London 1995, pp. 257-60, describe a method for recording and processing fingerprints on a hexagonally subdivided grid. There, sub-grids each comprising 7 individual hexagons arranged in a hexagon are processed in order to simplify a black-and-white image. A development of that method is described in a publication by R. Staunton: xe2x80x9cAn Analysis of Hexagonal Thinning Algorithms and Skeletal Shape Representationxe2x80x9d, in Pattern Recognition 29, 1131-46 (1996). The algorithm described there reduces wide lines in the image to the smallest possible width.
Weber et al., in xe2x80x9cOn the Application of the Neuron MOS Transistor Principle for Modern VLSI Designxe2x80x9d published in IEEE Transactions on Electron Devices 43, 1700-1708 (1996), describes transistor structures which make it possible to construct logic circuits with weightings of the input quantities.
The object of the invention is to provide an image acquisition apparatus which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which is suitable for application with small dimensions and which is suitable for acquiring and processing characteristics of a line structure of the image.
With the above and other objects in view there is provided, in accordance with the invention, an image acquisition apparatus, comprising:
a plurality of sensor elements arranged in a hexagonal grid dimensioned for acquiring a fingerprint sufficiently differentiated for identifying a person;
a plurality of processor elements each associated with a respective sensor element and integrated in accordance with the grid;
each of the processor elements having a memory unit for storing values;
each of the processor elements being connected to adjacent processor element in the grid for receiving values output by the adjacent processor elements;
the sensor elements being constructed for a capacitive measurement within a patterned, electrically conductive layer;
circuits associated with the sensor elements or the respectively assigned processor elements for generating a logic xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 depending on a capacitance ascertained by the sensor element;
the processor elements being adapted to store a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d; and
each of the processor elements being configured for implementing algorithms for:
a) setting the stored value from xe2x80x981xe2x80x99 to xe2x80x980xe2x80x99 if at most one connected processor element communicates a value xe2x80x981xe2x80x99;
b) setting the stored value from xe2x80x980xe2x80x99 to xe2x80x981xe2x80x99 if at least five connected processor elements communicate the value xe2x80x981xe2x80x99;
c) setting the stored value from xe2x80x981xe2x80x99 to xe2x80x980xe2x80x99 if at least two connected processor elements communicate the value xe2x80x981xe2x80x99;
d) setting the stored value from xe2x80x981xe2x80x99 to xe2x80x980xe2x80x99 if two connected processor elements of a first pair communicate the value xe2x80x981xe2x80x99 and two connected processor elements of a second pair communicate the value xe2x80x980xe2x80x99 and if the connected processor elements belonging to the same pair are adjacent to one another in the grid and are not adjacent to the processor elements of the respective other pair.
In accordance with an added feature of the invention, the storage units have at least one first storage device and one second storage device, and the processor elements are configured for storing, with respect to a measured value communicated by the sensor element, one of two possible values in the first storage device and the respective other possible value in the second storage device.
In accordance with an additional feature of the invention, each processor element is constructed with at least one neuron MOS circuit for weighting the values communicated by connected processor elements, arithmetically combining the values with one another, and feed the values to an evaluation circuit.
In accordance with another feature of the invention, the neuron MOS circuit comprises:
a first multiplexer with twelve inputs, enabled for a simultaneous changeover for selecting four of the inputs simultaneously in each case, and with four outputs;
a second multiplexer with eight inputs, enabled for a simultaneous changeover for selecting two of the input simultaneously in each case, and with two outputs;
the evaluation circuit with a first input and a second input connected to the outputs of the second multiplexer, and a further input via which the evaluation circuit can be caused to yield the logic value xe2x80x981xe2x80x99 if a value at the first input is greater than a value at the second input, and to instead yield the logic value xe2x80x981xe2x80x99 if the value at the first input is less than the value at the second input; and
six summers each two formed by respective pairs of neuron MOS transistors;
wherein the values supplied by the connected processor elements are fed to a first one of the summers and to the inputs of the first multiplexer, so that the values of two pairs of processor elements which are adjacent to one another, but are not adjacent to the respective other pair, are always present at the outputs of the first multiplexer; and
some of the summers being connected to the outputs of the first multiplexer and a respective pair of the summers or the sensor element being connected to simultaneously selected inputs of the second multiplexer such that the algorithms can be processed by changing over the multiplexers.
In accordance with a further feature of the invention, each processor element is constructed with at least one NMOS pass transistor logic circuit operating as a switch between a reference-ground potential and an evaluation circuit.
In accordance with again a further feature of the invention, the circuit includes:
first, second, third, fourth, and fifth functional blocks each comprising a number of NMOS transistors connected as one of AND gates and OR gates;
a multiplexer with one input and twelve outputs; and
a master-slave RS flip-flop for storing a state and for carrying out an evaluation; and
wherein the functional blocks are connected in parallel between the multiplexer and the master-slave RS flip-flop and only one functional block is at one time connected to the reference-ground potential via the multiplexer;
inputs for receiving the values communicated by the respectively connected the processor elements and complementary values thereof at the functional blocks;
wherein the first functional block short-circuits an input of the master flip-flop to the reference-ground potential if at least five of the six communicated values have the logic value xe2x80x981xe2x80x99
wherein the second functional block short-circuits an input of the master flip-flop to the reference-ground potential if at least five of the six communicated values have the logic value xe2x80x981xe2x80x99 and a signal at the output of the slave flip-flop has an intended logic value, the relevant input being selected by transistors using a global control quantity and a complement thereof;
wherein the third functional block short-circuits an input of the master flip-flop to the reference-ground potential if the communicated values of two connected processor elements of a first pair, the processor elements being selected by the multiplexer and being adjacent to one another, have the logic value xe2x80x981xe2x80x99 and the communicated values of two connected processor elements of a second pair, the processor elements being adjacent to one another and not being adjacent to the processor elements of the first pair, have the logic value xe2x80x980xe2x80x99;
wherein the fourth functional block short-circuits an input of the master flip-flop to the reference-ground potential depending on whether the communicated value of a connected processing element, selected by the multiplexer, has the logic value xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 in one of three directions provided; and
wherein the fifth functional block has a transistor controlled by the logic value supplied by the sensor element and by means of which an input of the master flip-flop is short-circuited to the reference-ground potential depending on the global control quantity and the complement thereof.
In the case of the apparatus according to the invention, an image, e.g. of a fingerprint, is acquired by means of a multiplicity of sensor elements arranged on a grid having a preferably hexagonal basic structure. A dedicated processor element is present for each sensor element, said processor element being arranged in the vicinity of the respective sensor element in accordance with the subdivisions of the grid. The-processor elements are provided for storing values which result from a measured value supplied by the sensor element, preferably a logic xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99, and for performing suitably implemented algorithms, in order to modify the stored value, if certain conditions on this value and values from storage devices of adjacent processor elements are met. These algorithms may be provided in particular for eliminating irregularities in the acquired image which are relevant to the acquisition of the basic structure. In addition, these algorithms can be used to emphasize the contours of the image more distinctly, e.g. by wide lines being reduced to a minimum standard width predetermined by the grid. If the apparatus is provided for acquiring and identifying fingerprints, evaluation algorithms may be implemented in the processing elements, which evaluation algorithms can be used to ascertain characteristic locations (minutiae such as e.g. end points and branchings of the lines) and compare them with stored references.
An individual element of the apparatus according to the invention therefore in each case contains a sensor element and a processor elementxe2x80x94provided for processingxe2x80x94with a storage unit. Such a unit of the apparatus can therefore be produced as a circuit by the methods for producing microelectronic components. Each processor element is connected to a group of processor elements that is in each case fixedly chosen from the rest of the processor elements, in such a way that the processor element can receive values communicated from the connected processor elements. Preferably, each processor element is connected in this way to the adjacent processor elements (six processor elements in the case of a hexagonal grid). The processor element forwards the value which is present in its storage unit to the (e.g. six) adjacent processor elements and receives, via an assigned input in each case, the value communicated from said processor elements, which value was stored by the respective adjacent processor element. The group of processor elements connected to a processor element need not necessarily include the processor element immediately adjacent to said processor element, but rather may additionally or exclusively include more remote processor elements in a manner adapted to the algorithms implemented in each case.
The connections between the processor elements are preferably formed by electrically conductive connections. The use of a grid formed by parketting using the same sized, preferably regular, hexagons as a basis for the arrangement of the individual units which each comprise a sensor element and a processor element has the advantage that the images are acquired particularly efficiently with regard to the further processing that is necessary. This results from the density of the parketting, the number of immediately adjacent neighbors and the symmetry present.
The particular advantage of the apparatus according to the invention resides in the fact that very small image structures can be acquired, since the units of which the apparatus is composed contain the processor elements and require only a small area. The processor elements operate completely in parallel and are controlled by global clock, supply and control lines. The global control lines enable the processor elements to be configured into a plurality of specific states each corresponding to a processing step by means of an algorithm. Owing to the integration of the processor elements within the grid provided for the image acquisition, the data processing speed is very high, and only a small amount of energy is consumed. Although each processor element can be realized as a low-power circuit and operates relatively slower in this case, a very good functionality (performance) of the entire system is achieved by the parallel processing.
In accordance with a concomitant feature of the invention, the outputs of the processor elements at the edge of the grid are fed back to a free input thereof, for establishing virtually mirror-symmetrical boundary conditions at the edges. The array of the arrangement can be read out sequentially by addressing circuits located at the edge.
An individual processor element forms a primitive automaton. It is provided with a storage device, in which a value assigned to a measured value of the sensor element can be stored, and also a logic circuit, which determines, from this value and the values from the connected processor elements which are present at the inputs of the processor element, a new valid value which is stored in the storage device instead of the old value. The processor element preferably has a storage unit having two state storage devices, only one of which is active in each case. By way of example, a logic xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 assigned to the measured value of the relevant sensor element may be stored in one storage device. The complementary value with respect thereto (that is say a logic xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99, respectively, in the example) is stored in the other storage device, with the result that the totality of these second storage devices contains the inverted image.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an image acquisition apparatus, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.